[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #24 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #23)
> Pushed a commit with your suggested fixes, however I don't think what I
> wrote makes sense, but since I don't understand b_in and c_in I tried follow
> what you did in OP_MTMSR.

:)

you're still thinking too much.  less brain, more automatonic robot :)

the bitassignnents look great.

however, with this:
                comb += self.o.msr.data.eq(b)
 171                 comb += self.o.msr.ok.eq(1)
 172 

you just trashed all the good work :)

lose those lines.


> Also, does OP_ADDPCIS need to be implemented? I cannot find it's
> implementation in microwatt.

correct, we leave it for now.

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