[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #23 from Cole Poirier <colepoirier at gmail.com> ---
Pushed a commit with your suggested fixes, however I don't think what I wrote
makes sense, but since I don't understand b_in and c_in I tried follow what you
did in OP_MTMSR.

Also, does OP_ADDPCIS need to be implemented? I cannot find it's implementation
in microwatt.

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