[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #25 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i added some more TODOs, and also translated the "if blah blah" in OP_MTMSR
which you can now look at and cookie-cut for OP_RFID.

also you missed srr1 in OP_SC.  remember to set srr1.ok.eq(1)

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