[libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=363

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
michael, i kinda need your help on this one.  soc/simple/test/test_core.py
is showing reg-reordering.  this *might* be possible to "fix" in VirtualRegPort
by inverting the concatenation order of the 8 registers to create the full
32-bit, rather than doing this in power_regspec_map.py:

        if name == 'full_cr': # full CR
            return e.read_cr_whole, 0b11111111, 0b11111111
        if name == 'cr_a': # CR A
            return e.read_cr1.ok, 1<<(7-e.read_cr1.data),
1<<(7-e.write_cr.data)

however i honestly have no idea what i'm doing, and would continue to
experiment
for several days, inverting bits until something worked.

or, it could just be that the CR regfile is not getting written to properl
(as in, the write-enable signals are not properly getting through).
i'll investigate that angle.

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