[libre-riscv-dev] [Bug 370] need a way to co-simulate hardware, qemu, microwatt, simulator, side-by-side

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=370

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #1)
> Cycle accurate - as in checking that the results are the same after every
> step?

cycle-accurate means that yes, you _could_ check that the results are the
same after every step through each and every instruction (not that you
absolutely
have to: it's just that it's possible to do so).

a JIT compiler (pearpc's JIT, qemu JIT) that is very specifically *not*
guaranteed to be the case, because several emulated instructions can end up
being
replaced by one (optimised) sequence of host-native instructions.

JIT-translated code would clearly be absolutely useless for us to attempt to
run and compare against, for that reason.

spike (the RISC-V simulator) went to a lot of trouble to even maintain
cycle-accurate emulation of the PTW, the MMU - pretty much everything,
*specifically* so that the software (BBL, linux kernel etc.) could be worked on
in parallel with development of some hardware, and the specification formalised
even before that.

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