[libre-riscv-dev] Understanding the LibreSOC core

[Yehowshua]

> On Jun 8, 2020, at 2:58 PM, Yehowshua <yimmanuel3 at gatech.edu> wrote:
> 
> Those look like reasonable numbers.
> 
> I think it should fit. At minimum, I can get it running
> inside the LiteX Verilator environment.
> 

Also do keep in mind that LiteX **requires the CPU to 
initialize the DDR3 present on the Versa.

Two ways to approach this:
1. I can strip the LiteX BIOS down to bare essentials for initializing DDR3 on the Versa, and the build that.
Once built, I can comb through the assembled binary looking for any instructions we don’t 
currently support.
2. We can use SDR on the ulx3s which requires no CPU intervention.

Yehowshua