[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #46 from Cole Poirier <colepoirier at gmail.com> ---
Ok. I think now the nmigen should match the microwatt VHDL, however, there may
be small errors as you made some modifications but left others for me to fix,
and I got confused about some of your comments re a_i, b_i, but I did my best
to interpret your comments while reading, line-by-line the vhdl from the
comments.

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