[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #44 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #41)
> I updated the unit test to deal with rdmaskn.
> 
> For how long rdmaskn must be held valid?

the entire time (the entire busy cycle)

> If I assert it for only one cycle,
> together with issue_i, it doesn't work. rel still rises on the next cycle.
> 
> Shouldn't it be latched, as with zero_a and imm_ok?

hmmm hmmm that's a really good point.  actually... it should be generated
from the Decoder2 information (Decode2Execute1 in power_decoder2.py),
and brought in via the CompXXXOpSubsets.

if it came in via those, it would be part of oper_i and would automatically
be latched.

it's *different* information depending on which Function Unit
is used, based on the regspecs which are collected together in
soc/fu/compunits/compunits.py (from soc/fu/*/pipe_data.py)

i'll need to think about it - can you set it manually for now and hold
it set for the duration of busy_o == True?

btw it should not be necessary to set the entire mask to all 1s, because
there does not exist an FU which takes zero operands.

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