[libre-riscv-dev] Yehowshua Tasks

[Yehowshua]

> also, parameterising of the minerva code so that address and data
> widths can be selected (128-bit, 64-bit, 32-bit)

Minerva cache can already do this.

Also, the way that Minerva does things is by having
`CachedLoadStoreUnit` contain the cache.
`CachedLoadStoreUnit` is also connected to the wishbone bus.

If I understand correctly, you would also want to follow this architecture?
If you can describe the interface you have in mind for the `CachedLoadStoreUnit`,
I can evaluate what is possible code-wise.

Yehowshua