[libre-riscv-dev] Yehowshua Tasks
yimmanuel3 at gatech.edu
Wed Jun 17 22:56:01 BST 2020
> also, parameterising of the minerva code so that address and data
> widths can be selected (128-bit, 64-bit, 32-bit)
Minerva cache can already do this.
Also, the way that Minerva does things is by having
`CachedLoadStoreUnit` contain the cache.
`CachedLoadStoreUnit` is also connected to the wishbone bus.
If I understand correctly, you would also want to follow this architecture?
If you can describe the interface you have in mind for the `CachedLoadStoreUnit`,
I can evaluate what is possible code-wise.
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