[libre-riscv-dev] libresoc memory architecture

[Cesar Strauss]

On 06/23/2020 19:14, Luke Kenneth Casson Leighton wrote:
> with the hardware providing the range-checking (and also enforcing the
> read/write by using the range-checking at the time of the write) we do
> not need to have an MMU at all in order to get testable code.
>
> this is really very simple and does not need any kludges.  as i said:
> the hardware *already exists* (in the Decoder) because the Decoder has
> to route the request to the right peripheral anyway.
>
> so the Decoder *knows* whether the address will succeed or not.  it's
> just that the "take-it-or-leave-it" Wishbone contract prevents and
> prohibits us from being able to do that check *unless* the actual
> request is performed.
>
> by which time it's too late as far as speculative execution is
> concerned: "damage" will have been done that is irreversible, and we
> are most definitely not going to do a Transaction / Rollback
> architecture, taking snapshots of memory.  that would be an insanely
> complex project.
>
> all that is needed is to expose that address-check information -
> information which *already exists* at the hardware level - via a
> "checker" function.
>
> this one very simple augmentation provides the means for us to turn
> the "take-it-or-leave-it" atomic-only single issue requests into
> "offer exchange complete" parallel-capable multi-issue speculative
> requests.

As I understand it, Wishbone has already a concept of an intelligent
"interconnect", which connects Masters to Slaves in the bus (it's not
necessarily a cross-bar, but it can be).

The role of this "interconnect" is to arbitrate masters, decode the
address, route the master CYC_O signal to the selected peripheral CYC_I,
and even raise a bus error in case the address is invalid.

So, I'm just saying that Wishbone has already a concept for the Decoder
function you just described above.

Furthermore, Wishbone has a pipelined transfer mode, where addresses and
data are presented in sequence, and the acknowledgements (or bus errors,
maybe) can come later, in order.

Wishbone tags maybe can be used for out-of-order acknowledgements, I think.

Regards,

Cesar