[libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=376

--- Comment #23 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #21)
> (In reply to Jacob Lifshay from comment #19)
> > > > Also, it might be worthwhile to add one more
> > > > core and disable one at manufacture time as a way to increase yield.
> > > 
> > > that's a good idea.  have to bear in mind that current leakage occurs
> > > regardless of whether the silicon is in use or not.
> > 
> > If we set up each core as a different power domain (which will also help
> > with idle power), the disabled core could be powered-down.
> 
> (you still get current leakage even when powered down, is my point)

I meant something like having a mosfet in the power line to the whole core, so
the entire power supply could be turned off. Assuming that mosfet wasn't
garbage, the power usage for the whole core could be reduced to the microwatt
level.

> > We should probably also widen the instruction decoders to decode 3 or 4
> > 32-bit instructions per cycle.
> 
> yes.  this will almost certainly be necessary, because we would have far more
> instructions to keep the monstrous number of RSes "fed".

We would also want to build a better branch predictor (TAGE?) since we would
have a higher power/area budget.

Both of those changes would potentially also drastically improve scalar
performance, approaching that of some modern desktop processors at equivalent
clock speeds.

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