[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #53 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #52)
> (In reply to Luke Kenneth Casson Leighton from comment #51)
> > i've removed the microwatt pseudocode because it now serves no purpose.
> > with microwatt using a_in, b_in and c_in as overloaded-lanes for incoming
> > SPRs, it it no longer useful.
> 
> Looks good. What can I do now. Is there something left to be done here or
> should I move on to another pipeline? 

> I apologize, I cannot determine this
> for myself by looking at fu/trap/main_stage.

nono, i've already started referencing the PDF.

two things (on this bugreport):

1) make a test_pipe_caller.py and remaining data structures/code.  (cookie-cut
an existing one, delete all the switch statements).  don't overwrite
pipe_data.py.  do cookie-cut a trap_input_data.py (cr_input_record.py)

2) add the pseudocode to sprset.mdwn (yes sprset.mdwn is a bad name) from
comment #47

https://libre-soc.org/openpower/isa/sprset/

or if you're bored of this one for a while, move on to
https://bugs.libre-soc.org/show_bug.cgi?id=348

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