[libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Jun 14 18:27:34 BST 2020


--- Comment #26 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #23)

> I meant something like having a mosfet in the power line to the whole core,
> so the entire power supply could be turned off. Assuming that mosfet wasn't
> garbage, the power usage for the whole core could be reduced to the
> microwatt level.

yep, as you can see from the list reply, i've caught up now.  with zero
power being applied between the VDD and VSS plane, the expectation would
be that there would be no current to actually leak.

this is the point at which my knowledge is lacking, and we'd have to ask
someone.  *nominally*, my understanding is that even powered down there
is still leakage, although because i did not ask that specific question
of the people who advised me, i can't confirm it.

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