[libre-riscv-dev] "simple" core

Cole Poirier colepoirier at gmail.com
Mon Jun 8 00:54:21 BST 2020

On Jun 7 2020, at 4:31 pm, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:

> the simple core is taking shape as a combination of all the pipelines,
> connected to the (5) types of register files.  all unit tests that
> have been developed to test *individual* pipelines have been borrowed
> through inheritance, to run against the register files, this time.
> you can try it out as:
> python3 soc/simple/test/test_core.py

Just ran it. SO COOL!!

> the next phases will involve:
> * adding in LDSTCompUnit
> * adding in minerva wishbone L1 I-Cache code (including bypass mode)
> * including the pre-written scoreboard "Instruction Queue" code
> * linking up NIA to the IQ, to fetch instructions and pass them to the decoder.
> at that point we will have an actual core that is capable of executing
> instructions on its own.  after that, we have a basis for carrying out
> further code-morphs, to add the precise-capable augmented scoreboard
> and so on.
> l.

Looking forward to seeing this all come together as the rest has so far.
And hopefully contributing a little :)


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