[libre-riscv-dev] LDST compunit semi operational

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Jun 10 18:27:56 BST 2020

i've managed to get the addresses split into LSBs and MSBs, and use the
lower 3 bits in conjunction with the Data Length for a bitmap mask on
writing, and as a corresponding bytemap mask for read.

this via the dummy / nonproduction L0CacheBuffer, which does not cope with
misalignment crossing a 64 bit boundary.

fortunately, nmigen Memory can be passed an *array* of write-enable lines,
and so can wishbone.

i could really use some help on this code as it is particularly complex and
also critical to get right.


crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

More information about the libre-riscv-dev mailing list