[libre-riscv-dev] daily kan-ban update 01jun2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Jun 2 11:11:11 BST 2020

On Tue, Jun 2, 2020 at 1:23 AM Cole Poirier <colepoirier at gmail.com> wrote:
> Today (actual):
> Spent today reading the parts of OPENPOWER ISA v3.1 related to traps,
> not finished yet. I don't understand very much currently, but I think
> that this will progress as I read and investigate further, however,
> since I don't think I can read the spec well enough to understand what I
> have to implement for fu/trap/main_stage, if someone else has the time I
> think they should do it. Otherwise, I'll continue to work away at
> understanding enough of the spec to be able to implement the trap pipeline.

it is not in the least bit necessary to "understand" the spec.  i do not.

what *is* necessary is to understand how to translate microwatt VHDL
source code into nmigen.

and to TRUST that microwatt is correct.

this is why i have put in code-snippets from microwatt into the bugreport.

this turns an exercise that would take months if not years by a factor
of approximately TEN.

quotes understanding quotes comes later.


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