[libre-riscv-dev] [Bug 372] create cycle-accurate JIT-compiler-based processor simulator

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=372

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |lkcl at lkcl.net

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #0)
> This could allow simulating our processor model much faster than most other
> methods.

pearpc already contains both a JIT and a cycle-accurate mode.
there is also power-gem5 which was recently updated to be capable of
running a linux kernel (and the 500mb/sec memory leak fixed).

both of these are written in c / c++ and are extremely fast.

is there a compelling reason to, using an appropriate colloquialism,
"reinvent the wheel?"

(the main purpose of deliberately writing the simulator in python was to get
"working knowledge" handle on POWER9 internals: it's served that
purpose extremely well, and also very deliberately uses the exact same
POWER instruction decoder as used in the hardware)

-- 
You are receiving this mail because:
You are on the CC list for the bug.