[libre-riscv-dev] AMD ISAs

Yehowshua yimmanuel3 at gatech.edu
Wed Jun 10 00:23:53 BST 2020

> On Jun 9, 2020, at 7:21 PM, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> in addition, we need to consider that the level of instruction
> compression (which reduces shared L1 I-Cache usage) anticipated
> through the hardware-level compression in SimpleV will be completely
> unobtainable for AMDGPU ISA interoperability... because we will be
> forced *to* have AMDGPU ISA interoperability.

This is a valid point.
I’ll get back to you on this.
I feel like there is a good way to do this...


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