[libre-riscv-dev] Understanding the LibreSOC core
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Mon Jun 8 19:55:41 BST 2020
On Mon, Jun 8, 2020 at 7:46 PM Yehowshua <yimmanuel3 at gatech.edu> wrote:
> > On Jun 8, 2020, at 2:24 PM, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> > yes absolutely! there is a EUR 10,000 budget allocated to this task:
> > https://bugs.libre-soc.org/show_bug.cgi?id=22 <https://bugs.libre-soc.org/show_bug.cgi?id=22>
> Hey Luke! I totally forgot about this.
> I should have my thesis done by end of June - crossing fingers.
> I would like to work on that - popping LibreSOC ontop of LiteX
*great*. by then that _should_ - as long as the wishbone interfaces
are up - be pretty straightforward to do.
> and stuffing it in my VersaECP5
oo i want one of those.
> - hope it fits - I’m a LiteX veteran at this point.
> This would be at the beginning of July.
> Can we get a gate count for this: http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/007828.html
> Here’s to hoping its below 400k - otherwise - yeah…
ok so i ran the following yosys commands:
$ python soc/simple/core.py
and it produced this:
=== top ===
Number of wires: 40844
Number of wire bits: 93864
Number of public wires: 5816
Number of public wire bits: 58836
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 42932
> libre-riscv-dev mailing list
> libre-riscv-dev at lists.libre-riscv.org
More information about the libre-riscv-dev