[libre-riscv-dev] libresoc memory architecture
programmerjake at gmail.com
Tue Jun 23 22:15:11 BST 2020
On Tue, Jun 23, 2020, 13:52 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> On Tue, Jun 23, 2020 at 9:02 PM Michael Nolan <mtnolan2640 at gmail.com>
> > On 6/23/20 3:52 PM, Luke Kenneth Casson Leighton wrote:
> > > question: where do the PowerISA MMU tables get the information from
> > > which bits are IO, RAM, or other?
> > >
> > > answer: they come from the information about the physical memory map.
> > Wouldn't they come from the software that sets up the page tables?
> and that software would need to read the information from somewhere,
> in order to know what it was, and consequently by another level of
> indirection we come back to that exact same hardware map function /
Your missing that the hardware map function doesn't need to be built in to
the memory system in the same way it is in RISC-V:
in RISC-V, the hardware address decoder is responsible for determining if a
particular address range is memory, i/o, not present, etc. which tells the
core if a particular access can be cached, write-combined, etc. Since it
controls if an access is cached or write-combined, it needs to be stuck in
the core so the core can know that it can cache or combine memory ops.
in Power, the hardware address decoder is only responsible for directing a
memory access to a particular peripheral or memory, the part that
determines if a particular address is cacheable or if memory accesses can
be combined is the page table entries stored in the MMU (the TLB
specifically), which is generic, it doesn't need to know the exact address
layout because that will be programmed by software. The software can get
that information from the boot rom, reading a device tree from the boot
drive (https://www.devicetree.org/), enumerating PCIe devices, reading ram
chips' config registers, and/or other methods. The method of getting that
information is *not* speed critical, since it's only retrieved at boot time
or when hardware is added/removed. This means that a Power core doesn't
need to be customized at the silicon level for each address layout since
that info is programmed into the MMU.
Admittedly, we will probably have to cludge something in there until we
have a sufficiently working MMU.
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