[libre-riscv-dev] [Bug 318] fix LDSTCompUnit
bugzilla-daemon at libre-soc.org
bugzilla-daemon at libre-soc.org
Fri Jun 12 12:13:13 BST 2020
https://bugs.libre-soc.org/show_bug.cgi?id=318
--- Comment #27 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #26)
> In store():
>
> 538 if imm_ok:
> 539 yield dut.rd.go.eq(0b101)
> 540 else:
> 541 yield dut.rd.go.eq(0b111)
> 542 yield from wait_for(dut.rd.rel)
> 543 yield dut.rd.go.eq(0)
>
> Another case of multi-cycle assertion of go.
it works... it is however just a coincidence.
> This time, since there are multiple independent rel signals to wait for, a
> parallel test is the sensible way to go.
>
> I'll go ahead and implement it.
yes please. keep it as a separate test.
>
> I intend to do it in a general way, that will apply whenever you need to
> test a rel/go port.
oh good. it applies to ADR as well as ST so yes.
a base class that can be instantiated, this would be very handy.
> In both cases, the rel->go delay will be parameterized, including a no-delay
> case.
yes. like it.
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