[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Jun 7 07:11:44 BST 2020


--- Comment #75 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
commit d2e0e6bea57795fb522e0805b16e6f2852472f98
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Sun Jun 7 07:03:58 2020 +0100

    add MSR to simulator context

as comment says.  i also updated the git submodule so that sprset now
contains the (new, untested) mtmsr/mfmsr.  if you rerun pywriter.py
you'll see the code now gets created.

and that in turn means that if you add a unit test that uses mfmsr
or mtmsr, the code in the auto-generated sprset.py for op_mfmsr/op_mtmsr
will get called.

whether that (completely untested) code is *accurate* or not is another matter.

we now have a situation of two "unknowns"

1. unknown simulator
2. unknown hardware code.

the normal solution for this is to "call in" something that *is* known,
and that would be the qemu emulator.  except we kinda need some help from
michael to do that in a short timescale, or we need to investigate it
in a longer one.  given that there's a critical task needed (investigating
the CR bit-ordering) i'd rather we not pull him off of that.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list