[libre-riscv-dev] [Bug 383] New: Complete first functional POWER9 Core

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Jun 14 19:23:10 BST 2020


            Bug ID: 383
           Summary: Complete first functional POWER9 Core
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

After the decision to implement POWER9 instead of RISC-V a full from-scratch
implementation of POWER9 was needed in nmigen.  This to become the later basis
for adding Vectorisation, GPU and VPU instructions.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list