[libre-riscv-dev] [Bug 377] possible bug in Simulator Mem ld/st function

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=377

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
problem "solved":

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index f76afda..7dfcec1 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -51,6 +51,7 @@ class Mem:
     def _get_shifter_mask(self, wid, remainder):
         shifter = ((self.bytes_per_word - wid) - remainder) * \
             8  # bits per byte
+        shifter = remainder * 8
         mask = (1 << (wid * 8)) - 1
         print ("width,rem,shift,mask", wid, remainder, hex(shifter),
hex(mask))
         return shifter, mask

is this something that we need to put under the control of a BE/LE MSR flag?

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