[libre-riscv-dev] test issuer core now functional, running loops

[Luke Kenneth Casson Leighton]

i've just managed to get the test issuer "basic" core to actually run
a loop involving a branch conditional.
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/issuer.py;h=e41bc65248c4030bdf80c1b0e079d56f2cb60f5a;hb=HEAD#l126

despite the fact that the instruction memory is a 16 word SRAM and the
LD/ST interface also connects directly to a 64 dword SRAM, this is a
huge deal as it is the first time that any kind of demonstration of
the ability to execute *any* kind of loop has occurred.

the only difficulty was in finding a source of information (a signal)
that indicated that the branch unit had updated the program counter.
this was actually very easy to find: the FastRegs regfile
"write-enable" signal!  by monitoring that signal we can also tell if
the Trap pipeline likewise altered the PC.

thanks to michael's help, given that branch and link is also
implemented (and the unit tests confirm it for several weeks), it is
not unreasonable to expect that function calls will also simply
"work".

the focus now needs to be on:

* L1 Data Cache  and and stand-alone unit tests
* L1 Instruction Cache and stand-alone unit tests
* wishbone connectivity to those and stand-alone unit tests confirming
functionality from the *other* end of a WB Bus
* integration into the test core whilst also leaving the option to run
the much smaller SRAM variant

l.

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