[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Jun 7 23:34:24 BST 2020


--- Comment #85 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #83)
> (In reply to Cole Poirier from comment #81)
> > (In reply to Luke Kenneth Casson Leighton from comment #80)
> i basically disregarded entirely the statement at the top of the POWER v3.0B
> PDF, "this pseudocode is in no way intended to be an executable language"
> and did exactly that.  teehee

Seems to have saved us many months of work!

> > Ah, so just translating that
> > psuedo code into the TRAP method of ISACaller?
> yeeees :)

Makes sense :)

> so i saw the latest commit, and added some TODO comments.  if you
> can do them *at the same time* as actually adding things in
> caller.py ISACAller.TRAP, then you will see clearly the direct connection
> between the two.

Perfect, will do.

> oh - yes, add a test_twi (or test_tdi) as well, you will have to
> set an initial register RA, such as:
>             initial_regs = [0] * 32
>             initial_regs[2] = random.randint(0, (1<<32)-1)
> or maybe do a fixed number, initially, so you know exactly what
> you are testing against.  remember if you set initial_regs[2]
> then that means that "RA" in the instruction has to be 2.
> from fixedtrap.mdwn:
> D-Form
> * twi TO,RA,SI
> therefore, what you put in the listing, would have to be twi TO,-->2<--,SI
> TO is a bitfield, saying whether you want to compare equals, greater,
> less-than etc. etc.
> SI is an immediate that you want to compare against register RA.
> so just pick something that, *manually*, you know will be "equal", or
> something.

Thanks, very helpful, will do as well.

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