[libre-riscv-dev] Yehowshua Tasks
yimmanuel3 at gatech.edu
Tue Jun 16 14:50:30 BST 2020
> it is *not* ok to have phase 1 proceed, the notification go back, "yes
> there is room in the cache for you" followed in phase 2 "actually i lied,
> we need to raise an exception now”.
Right. So I read through the Minerva cache and understand about
98% of it. There is a cache miss signal. And also a bus error signal
for example, if the cache tries to flush to the main memory via the
wishbone bus and it fails, it will raise bus_err.
What is the difference between hold off and go die?
I’m trying to write a simple unit bench for minerva L1Cache today.
Is there an NLNet task covering this?
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