[libre-riscv-dev] Scoreboard and LDST questions

[Cole Poirier]

On Jun 20 2020, at 7:46 pm, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:

> everything - all three possible arrangements - is *specifically* allocated
> so that there are AT THE VERY MINIMUM at LEAST three Computational Units
> running and in DIFFERENT phases.
> 
> * one CU will be in op issue phase.
> * one CU will be in src read phase
> * one CU will be in dest write phase.
> 
> by having these THREE CUs (aka RSes) active, one of them *will* become free
> in any clock cycle: that free CU may therefore accept the current
> instruction and therefore there will be no stalling.
> 
> therefore we achieve 1 IPC.
> 
> that is of course assuming that there are no hazards.
> 
> if hazards exist those 3 CUs are inadequate because one of them will block,
> waiting for the output from one other CU.
> 
> therefore we put lots more CUs down (at least twice more).

Star. Saving this to add to/integrate with our internal documentation.