[libre-riscv-dev] Contributing to the Libre-Soc Project
yimmanuel3 at gatech.edu
Sun Jun 7 00:03:36 BST 2020
> On Jun 6, 2020, at 6:29 PM, Sanjay Menon <sanjayamenon.mec at gmail.com> wrote:
> I am a budding VLSI enthusiast and open-source developer. I would love to
> work with the team in your goal to achieve a completely open source project.
My response will be quick as I spend my weekends writing my Master’s
Hi. And fantastic. We have a charter, that you should review here:
> I believe that as a beginner in this area, I would be able to learn more
> from you guys as I contribute to this wonderful project.
Sure. Would probably start by learning nMigen as it seems you’re coming
from a verilog background.
At the moment, we’re prepping for the Oct/Nov 2020 Tapeout.
Most of the work is going into hooking up the scoreboard to
our functional units right now.
We also make extensive use of formal verification.
Which reminds me, we need to separate FHDLTestCase class
into the nmutils repo since it's no longer officially maintained.
That’s a pretty simple task - maybe something you could handle.
You’ll know what I mean once you start playing with nMigen.
We also should start putting test we want to in `__init__.py` in the soc/tests
folder - so that `setup.py test` works.
So much to do, the aforementioned tasks are pretty beginner level.
> I thank Yehowshua Immanuel for introducing me to this project. Can't wait
> to start already. Hoping to hear from you soon.
> To know more about me do checkout my LinkedIn
> <http://www.linkedin.com/in/sanjay-menon-91791815a> profile.
> Thanks and regards,
> Sanjay A Menon
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> libre-riscv-dev at lists.libre-riscv.org
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