[libre-riscv-dev] daily kan-ban update 11jun2020
cestrauss at gmail.com
Thu Jun 11 22:02:18 BST 2020
* Work on the parallel test concept in
* Implement proper ready / valid signaling on the test ALU at
* Looking into compldst_multi.py's unit tests to confirm that they are
* (off-project): git bisecting systemd due to getting system freezes
after an upgrade. Fun.
Interesting tools and readings, to share:
* Pipelined Skid Buffer
The circuit itself is useful, for meeting timing on long pipelines. But,
specially, I find it a nice example of the Finite State Machine (FSM)
technique, from requirements, concept and diagram, to design and
implementation. Doesn't cover unit tests and formal proofs, though.
* GTKWave package, from the PyVCD module
While used in a limited way by nMigen itself, for pre-filling traces in
a GTKWave window, it can do much more: comments, blank separators, trace
colors, scale, etc.
* Synchronous Resets? Asynchronous Resets? I am so confused! How will I
ever know which to use? by Clifford E. Cummings
* Clock Domain Crossing (CDC) Design & Verification Techniques Using
SystemVerilog, by Clifford E. Cummings
In particular, see section 5.8.2: Multi-bit CDC signal passing using
1-deep / 2-register FIFO synchronizer.
* Understanding Latency Hiding on GPUs, by Vasily Volkov
Nice introductory chapter on internal GPU architecture.
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