June 2019 Archives by author

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Starting: Sat Jun 1 00:15:46 BST 2019
Ending: Sun Jun 30 20:07:22 BST 2019
Messages: 340

• [libre-riscv-dev] sponsorship from puri.sm   Hendrik Boom
• [libre-riscv-dev] KCP53000B micro-architecture thoughts   Samuel Falvo II
• [libre-riscv-dev] KCP53000B micro-architecture thoughts   Samuel Falvo II
• [libre-riscv-dev] KCP53000B micro-architecture thoughts   Samuel Falvo II
• [libre-riscv-dev] KCP53000B micro-architecture thoughts   Samuel Falvo II
• [libre-riscv-dev] KCP53000B micro-architecture thoughts   Samuel Falvo II
• [libre-riscv-dev] LD/ST address matcher   Samuel Falvo II
• [libre-riscv-dev] A little introduction   Samuel Falvo II
• [libre-riscv-dev] store computation unit   Samuel Falvo II
• [libre-riscv-dev] System-Wide Complexity Rant (was store computation unit)   Samuel Falvo II
• [libre-riscv-dev] System-Wide Complexity Rant (was store computation unit)   Samuel Falvo II
• [libre-riscv-dev] System-Wide Complexity Rant (was store computation unit)   Samuel Falvo II
• [libre-riscv-dev] Phoronix reported on latest CroudSupply update   Samuel Falvo II
• [libre-riscv-dev] Introducing Myself   Samuel Falvo II
• [libre-riscv-dev] [Bug 93] add Cache-as-ram mode for boot   Samuel Falvo II
• [libre-riscv-dev] System-Wide Complexity Rant (was store computation unit)   Samuel Falvo II
• [libre-riscv-dev] Paper: Scoreboards can deadlock   Samuel Falvo II
• [libre-riscv-dev] store computation unit   Samuel Falvo II
• [libre-riscv-dev] Paper: Scoreboards can deadlock   Samuel Falvo II
• [libre-riscv-dev] Leaving the project   Aleksandar Kostovic
• [libre-riscv-dev] KCP53000B micro-architecture thoughts   Luke Kenneth Casson Leighton
• [libre-riscv-dev] KCP53000B micro-architecture thoughts   Luke Kenneth Casson Leighton
• [libre-riscv-dev] KCP53000B micro-architecture thoughts   Luke Kenneth Casson Leighton
• [libre-riscv-dev] store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] KCP53000B micro-architecture thoughts   Luke Kenneth Casson Leighton
• [libre-riscv-dev] KCP53000B micro-architecture thoughts   Luke Kenneth Casson Leighton
• [libre-riscv-dev] store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] KCP53000B micro-architecture thoughts   Luke Kenneth Casson Leighton
• [libre-riscv-dev] slashdot   Luke Kenneth Casson Leighton
• [libre-riscv-dev] KCP53000B micro-architecture thoughts   Luke Kenneth Casson Leighton
• [libre-riscv-dev] KCP53000B micro-architecture thoughts   Luke Kenneth Casson Leighton
• [libre-riscv-dev] LD/ST address matcher   Luke Kenneth Casson Leighton
• [libre-riscv-dev] store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] LD/ST address matcher   Luke Kenneth Casson Leighton
• [libre-riscv-dev] store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] LD/ST address matcher   Luke Kenneth Casson Leighton
• [libre-riscv-dev] A little introduction   Luke Kenneth Casson Leighton
• [libre-riscv-dev] LD/ST address matcher   Luke Kenneth Casson Leighton
• [libre-riscv-dev] LD/ST address matcher   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Fwd: store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] LD/ST address matcher   Luke Kenneth Casson Leighton
• [libre-riscv-dev] LD/ST address matcher   Luke Kenneth Casson Leighton
• [libre-riscv-dev] LD/ST address matcher   Luke Kenneth Casson Leighton
• [libre-riscv-dev] store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] LD/ST address matcher   Luke Kenneth Casson Leighton
• [libre-riscv-dev] KCP53000B micro-architecture thoughts   Luke Kenneth Casson Leighton
• [libre-riscv-dev] store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] LD/ST address matcher   Luke Kenneth Casson Leighton
• [libre-riscv-dev] A little introduction   Luke Kenneth Casson Leighton
• [libre-riscv-dev] LD/ST address matcher   Luke Kenneth Casson Leighton
• [libre-riscv-dev] LD/ST address matcher   Luke Kenneth Casson Leighton
• [libre-riscv-dev] store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] texture opcodes   Luke Kenneth Casson Leighton
• [libre-riscv-dev] outstanding commit pending counters (for multi issue)   Luke Kenneth Casson Leighton
• [libre-riscv-dev] what was the idea that needed to be recorded in the bugtracker?   Luke Kenneth Casson Leighton
• [libre-riscv-dev] store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] what was the idea that needed to be recorded in the bugtracker?   Luke Kenneth Casson Leighton
• [libre-riscv-dev] LD/ST address matcher   Luke Kenneth Casson Leighton
• [libre-riscv-dev] System-Wide Complexity Rant (was store computation unit)   Luke Kenneth Casson Leighton
• [libre-riscv-dev] LD/ST address matcher   Luke Kenneth Casson Leighton
• [libre-riscv-dev] System-Wide Complexity Rant (was store computation unit)   Luke Kenneth Casson Leighton
• [libre-riscv-dev] System-Wide Complexity Rant (was store computation unit)   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Phoronix reported on latest CroudSupply update   Luke Kenneth Casson Leighton
• [libre-riscv-dev] croudsupply   Luke Kenneth Casson Leighton
• [libre-riscv-dev] LD/ST address matcher   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introducing Myself   Luke Kenneth Casson Leighton
• [libre-riscv-dev] System-Wide Complexity Rant (was store computation unit)   Luke Kenneth Casson Leighton
• [libre-riscv-dev] System-Wide Complexity Rant (was store computation unit)   Luke Kenneth Casson Leighton
• [libre-riscv-dev] [Bug 92] Implement in order instruction retire refcounting   Luke Kenneth Casson Leighton
• [libre-riscv-dev] outstanding commit pending counters (for multi issue)   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Paper: Scoreboards can deadlock   Luke Kenneth Casson Leighton
• [libre-riscv-dev] outstanding commit pending counters (for multi issue)   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introducing Myself   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Paper: Scoreboards can deadlock   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introducing Myself   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introducing Myself   Luke Kenneth Casson Leighton
• [libre-riscv-dev] store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Leaving the project   Luke Kenneth Casson Leighton
• [libre-riscv-dev] store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Paper: Scoreboards can deadlock   Luke Kenneth Casson Leighton
• [libre-riscv-dev] store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] isamux   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Safety Critical support   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Safety Critical support   Luke Kenneth Casson Leighton
• [libre-riscv-dev] test please ignore, BATV added to exim4   Luke Kenneth Casson Leighton
• [libre-riscv-dev] test please ignore, BATV added to exim4   Luke Kenneth Casson Leighton
• [libre-riscv-dev] libre-riscv.org attacked through exim4   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] ModuleNotFoundError in soc.git   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] wiki usability issues   Luke Kenneth Casson Leighton
• [libre-riscv-dev] wiki usability issues   Luke Kenneth Casson Leighton
• [libre-riscv-dev] wiki usability issues   Luke Kenneth Casson Leighton
• [libre-riscv-dev] wiki usability issues   Luke Kenneth Casson Leighton
• [libre-riscv-dev] ModuleNotFoundError in soc.git   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] test please ignore   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Fwd: store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sponsorship from puri.sm   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV VLIW format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV VLIW format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sponsorship from puri.sm   Luke Kenneth Casson Leighton
• [libre-riscv-dev] store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] VL concept   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV VLIW format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] store computation unit   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV Prefix questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV Prefix questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV Prefix questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV Prefix questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] vliw idea naming   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] fault-only-first mode   Luke Kenneth Casson Leighton
• [libre-riscv-dev] uniform instruction format   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Virtual Memory Management system   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV Prefix questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV Prefix questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV Prefix questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV Prefix questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV Prefix questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sv specs   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sv swizzle constants   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV Prefix questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sv specs   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sv swizzle constants   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV Prefix questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV Prefix questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV Prefix questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV Prefix questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV Prefix questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV Prefix questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV Prefix questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV Prefix questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV Prefix questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV Prefix questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV Prefix questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV Prefix questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] SV Prefix questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Virtual Memory Management system   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sv spike simulator   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sv spike simulator   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sv spike simulator   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sv spike simulator   Luke Kenneth Casson Leighton
• [libre-riscv-dev] VBLOCK Format, FSM Decoder   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sv.setvl encoding   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sv.setvl encoding   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sv.setvl encoding   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sv.setvl encoding   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sv.setvl encoding   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sv.setvl encoding   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sv.setvl encoding   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sv.setvl encoding   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sv.setvl encoding   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sv.setvl encoding   Luke Kenneth Casson Leighton
• [libre-riscv-dev] div/mod algorithm written in python   Luke Kenneth Casson Leighton
• [libre-riscv-dev] div/mod algorithm written in python   Luke Kenneth Casson Leighton
• [libre-riscv-dev] re-using the FP pipelines for INT   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sv.setvl encoding   Luke Kenneth Casson Leighton
• [libre-riscv-dev] div/mod algorithm written in python   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sv-prefix RVC   Luke Kenneth Casson Leighton
• [libre-riscv-dev] nmigen version 0.1 in progress   Luke Kenneth Casson Leighton
• [libre-riscv-dev] KCP53000B micro-architecture thoughts   Jacob Lifshay
• [libre-riscv-dev] LD/ST address matcher   Jacob Lifshay
• [libre-riscv-dev] LD/ST address matcher   Jacob Lifshay
• [libre-riscv-dev] A little introduction   Jacob Lifshay
• [libre-riscv-dev] LD/ST address matcher   Jacob Lifshay
• [libre-riscv-dev] LD/ST address matcher   Jacob Lifshay
• [libre-riscv-dev] LD/ST address matcher   Jacob Lifshay
• [libre-riscv-dev] LD/ST address matcher   Jacob Lifshay
• [libre-riscv-dev] LD/ST address matcher   Jacob Lifshay
• [libre-riscv-dev] LD/ST address matcher   Jacob Lifshay
• [libre-riscv-dev] LD/ST address matcher   Jacob Lifshay
• [libre-riscv-dev] LD/ST address matcher   Jacob Lifshay
• [libre-riscv-dev] what was the idea that needed to be recorded in the bugtracker?   Jacob Lifshay
• [libre-riscv-dev] LD/ST address matcher   Jacob Lifshay
• [libre-riscv-dev] texture opcodes   Jacob Lifshay
• [libre-riscv-dev] LD/ST address matcher   Jacob Lifshay
• [libre-riscv-dev] System-Wide Complexity Rant (was store computation unit)   Jacob Lifshay
• [libre-riscv-dev] System-Wide Complexity Rant (was store computation unit)   Jacob Lifshay
• [libre-riscv-dev] Phoronix reported on latest CroudSupply update   Jacob Lifshay
• [libre-riscv-dev] croudsupply   Jacob Lifshay
• [libre-riscv-dev] Introducing Myself   Jacob Lifshay
• [libre-riscv-dev] Leaving the project   Jacob Lifshay
• [libre-riscv-dev] uniform instruction format   Jacob Lifshay
• [libre-riscv-dev] uniform instruction format   Jacob Lifshay
• [libre-riscv-dev] uniform instruction format   Jacob Lifshay
• [libre-riscv-dev] Safety Critical support   Jacob Lifshay
• [libre-riscv-dev] Safety Critical support   Jacob Lifshay
• [libre-riscv-dev] Safety Critical support   Jacob Lifshay
• [libre-riscv-dev] Who heard about the EPI before ?   Jacob Lifshay
• [libre-riscv-dev] libre-riscv.org attacked through exim4   Jacob Lifshay
• [libre-riscv-dev] uniform instruction format   Jacob Lifshay
• [libre-riscv-dev] uniform instruction format   Jacob Lifshay
• [libre-riscv-dev] uniform instruction format   Jacob Lifshay
• [libre-riscv-dev] uniform instruction format   Jacob Lifshay
• [libre-riscv-dev] uniform instruction format   Jacob Lifshay
• [libre-riscv-dev] uniform instruction format   Jacob Lifshay
• [libre-riscv-dev] wiki usability issues   Jacob Lifshay
• [libre-riscv-dev] wiki usability issues   Jacob Lifshay
• [libre-riscv-dev] wiki usability issues   Jacob Lifshay
• [libre-riscv-dev] uniform instruction format   Jacob Lifshay
• [libre-riscv-dev] vliw idea naming   Jacob Lifshay
• [libre-riscv-dev] uniform instruction format   Jacob Lifshay
• [libre-riscv-dev] SV Prefix questions   Jacob Lifshay
• [libre-riscv-dev] SV Prefix questions   Jacob Lifshay
• [libre-riscv-dev] SV Prefix questions   Jacob Lifshay
• [libre-riscv-dev] SV Prefix questions   Jacob Lifshay
• [libre-riscv-dev] sv specs   Jacob Lifshay
• [libre-riscv-dev] sv swizzle constants   Jacob Lifshay
• [libre-riscv-dev] SV Prefix questions   Jacob Lifshay
• [libre-riscv-dev] SV Prefix questions   Jacob Lifshay
• [libre-riscv-dev] SV Prefix questions   Jacob Lifshay
• [libre-riscv-dev] SV Prefix questions   Jacob Lifshay
• [libre-riscv-dev] SV Prefix questions   Jacob Lifshay
• [libre-riscv-dev] SV Prefix questions   Jacob Lifshay
• [libre-riscv-dev] SV Prefix questions   Jacob Lifshay
• [libre-riscv-dev] SV Prefix questions   Jacob Lifshay
• [libre-riscv-dev] sv spike simulator   Jacob Lifshay
• [libre-riscv-dev] sv.setvl encoding   Jacob Lifshay
• [libre-riscv-dev] sv.setvl encoding   Jacob Lifshay
• [libre-riscv-dev] sv.setvl encoding   Jacob Lifshay
• [libre-riscv-dev] div/mod algorithm written in python   Jacob Lifshay
• [libre-riscv-dev] div/mod algorithm written in python   Jacob Lifshay
• [libre-riscv-dev] div/mod algorithm written in python   Jacob Lifshay
• [libre-riscv-dev] nmigen version 0.1 in progress   Jacob Lifshay
• [libre-riscv-dev] Introducing Myself   Tobias Platen
• [libre-riscv-dev] Introducing Myself   Tobias Platen
• [libre-riscv-dev] Introducing Myself   Tobias Platen
• [libre-riscv-dev] ModuleNotFoundError in soc.git   Tobias Platen
• [libre-riscv-dev] Virtual Memory Management system   Tobias Platen
• [libre-riscv-dev] A little introduction   whygee at f-cpu.org
• [libre-riscv-dev] A little introduction   whygee at f-cpu.org
• [libre-riscv-dev] LD/ST address matcher   whygee at f-cpu.org
• [libre-riscv-dev] A little introduction   whygee at f-cpu.org
• [libre-riscv-dev] LD/ST address matcher   whygee at f-cpu.org
• [libre-riscv-dev] Introducing Myself   whygee at f-cpu.org
• [libre-riscv-dev] Introducing Myself   whygee at f-cpu.org
• [libre-riscv-dev] Safety Critical support   whygee at f-cpu.org
• [libre-riscv-dev] Who heard about the EPI before ?   whygee at f-cpu.org
• [libre-riscv-dev] Who heard about the EPI before ?   whygee at f-cpu.org
• [libre-riscv-dev] [Bug 78] IEEE754 FP "div" needed   whygee at f-cpu.org
• [libre-riscv-dev] [Bug 91] New: Design and implement Texturing 3D opcodes   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 91] Design and implement Texturing 3D opcodes   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 92] New: Implement in order instruction retire refcounting   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 91] Design and implement texturing opcodes for 3D graphics   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 93] New: add Cache-as-ram mode for boot   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 93] add Cache-as-ram mode for boot   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 92] Implement in order instruction retire refcounting   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 92] Implement in order instruction retire refcounting   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 92] Implement in order instruction retire refcounting   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 92] Implement in order instruction retire refcounting   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 92] Implement in order instruction retire refcounting   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 94] New: implement load/store memory dependency matrix   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 94] implement load/store memory dependency matrix   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 95] New: implement shadowing for use in precise exceptions, branch speculation, predication and WaW ordering   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 91] Design and implement texturing opcodes for 3D graphics   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 96] New: Add AES, SHA1, SHA256, and SHA3 instructions   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 73] all nmigen module-based classes now need to derive from Elaboratable   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 95] implement shadowing for use in precise exceptions, branch speculation, predication and WaW ordering   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 97] New: FP16 mul bug   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 97] FP16 mul bug   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 78] IEEE754 FP "div" needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 78] IEEE754 FP "div" needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 78] IEEE754 FP "div" needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 78] IEEE754 FP "div" needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 92] Implement in order instruction retire refcounting   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 98] New: determine if Sleef can be used for SIMD math algorithms in Kazan   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 99] New: IEEE754 *pipelined* FPDIV unit needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 44] IEEE754 FPU inverse-sqrt   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 44] IEEE754 FPU inverse-sqrt   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 88] investigate multi-issue (superscalar)   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 100] New: Investigate if Flush-to-zero mode for denormal handling is needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 100] Investigate if Flush-to-zero mode for denormal handling is needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 44] IEEE754 FPU inverse-sqrt   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 44] IEEE754 FPU inverse-sqrt   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 44] IEEE754 FPU inverse-sqrt   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 44] IEEE754 FPU inverse-sqrt   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 44] IEEE754 FPU inverse-sqrt   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 44] IEEE754 FPU inverse-sqrt   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 101] New: IEE754 pipeline "go_die" (Computation Unit Cancellation) needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 102] New: IEEE754 pipeline "early out" needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 101] IEEE754 pipeline "go_die" (Computation Unit Cancellation) needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 101] IEEE754 pipeline "go_die" (Computation Unit Cancellation) needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 103] New: Ensure that all source code actually has a copyright license   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 103] Ensure that all source code actually has a copyright license   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 104] New: add subvl support from latest sv 0.6 draft spec   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 105] New: sv 0.6 draft support for fail-on-first condition (and trap)   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed   bugzilla-daemon at libre-riscv.org
• [libre-riscv-dev] [Bug 106] New: pipeline early-in, early-out on concurrent function units   bugzilla-daemon at libre-riscv.org

Last message date: Sun Jun 30 20:07:22 BST 2019
Archived on: Sun Jun 30 20:07:45 BST 2019

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