[libre-riscv-dev] uniform instruction format
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun Jun 16 19:16:46 BST 2019
oh, btw, jacob: twin-predication is *really* important to fit into the
48/64-bit format. having 3 4 5 or 6 predication registers is
*NOWHERE* near as high a priority.
twin predication (separate optional predicate for source, separate
optional predicate for destination), in an utterly deceptively simple
way, turns all of LD, ST, MV and FCVT into VSPLAT, VREDUCE, VINSERT,
VGATHER, VSCATTER and so on with *ZERO* additional opcodes.
to repeat that again.
with NO ADDITIONAL OPCODES, *all* of the two-operand instructions that
were never designed or intended for use as vector instructions, are
turned into the most incredibly powerful vectorised operations
covering the *FULL* range *AND BEYOND* of *ALL* vector operations that
normally require a massive plethora of specialist vector opcodes to
it would be almost irresponsible not to provide this capability.
thus, the gather/scatter "lsk" can be removed, as it is covered by
twin-predication, and an extra instruction to provide gather/scatter
is NOT required.
to provide proper twin-predication, each predicate ideally must be 2
bits, for a total of 4 bits:
* 00 - disabled (no predication)
* 01 - enabled (on register xN)
* 10 - TBD (there's no point having disabled-inverted)
* 11 - inverted (on register xN)
however *might* be possible to fit twin-predication into only 3 bits,
sacrificing some of the combinations (src-inverted, dest not;
dest-inverted, src not).
* 000 - disabled (no predication on src or dest)
* 001 - enabled on src, disabled on dest
* 010 - enabled on dest, disabled on src
* 011 - enabled on src, enabled on dest
* 100 - TBD (reserved?)
* 101 - inverted on src, disabled on dest
* 110 - disabled on src, inverted on dest
* 111 - inverted on src, inverted on dest
with no need for lsk=0b0001, the LSK table may be moved up by one,
leaving lsk=0b0111 to specify "strided with a stride in bytes
specified by s0", and lsk reduced to 3 bits in size.
this is so absolutely critical that where vitp6 has pred=0, that
cannot be allowed to be the case, and one of the extra "reserved" bits
in P48-I made available for pred. these use rd and rs1 so are most
likely to be instruction types that have twin-predication.
this can be resolved by adding a vitp7 format, where vitp6 (and vtp5)
remain for the single-predication instrictions.
for P48-R-Type, these are *not* twin-predication-capable, they are
dual-opcode into a single dest, so vitp6 is fine for them. likewise
P48-U-type: twin-predication doesn't make sense because there is only
a dest reg (rd).
this is sufficiently important that resolving fitting vitp7 into
P48-LD-Type and P48-ST-Type is worthwhile using bit 6 (otherwise
yes, vitp7 has to have the full range of twin-predicate bits, no lsk
cannot really be compressed any more than it is (unless it's reduced
to 2 bits: continuous, 2x, something-else-x, stride=x8)
More information about the libre-riscv-dev