[libre-riscv-dev] uniform instruction format
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun Jun 16 11:05:51 BST 2019
split out into separate tables.
* bits 17:0 now fit into a sane width, in their own separate table.
* another table specifies the correspondance between 32-bit and 48-bit
formats. basically RV32 shifted by 16 bits.
* a sub-table where there's no correspondance between RV32-*-Type and
* another table that can be used to expand the P48-*-Types to P64-*-Types
in this last table there's room for both VL *and* VStart - both of which
are crucial to pass in (not just VL).
i *assumed* that P48-R the imm bits were an error and mapped it to
btw, VStart is not slow at all. all that happens in our design is: VStart
is unary-encoded, 1 is subtracted from that, and the result of that
arithmetic operation is ANDed with the predicate [which if not specified
defaults to "all 1s"]
that's then chucked at the vectorisation multi-issue engine, and the
predication shadow system sorts it out from there.
very very simple, and not in the slightest bit "slow".
so, with this encoding, which despite being an internal format, could
actually fit into 64 bits: can you see how i was expecting it to take an
absolute maximum of 1-2 days? it's been... under an hour's work.
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