[libre-riscv-dev] uniform instruction format
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun Jun 16 10:28:10 BST 2019
i added (below each corresponding line, and separately), the RV32 formats
R/S/I/U/FR4/FR) and *sigh* it's easier to look at the original file, in a
large editor window.
the only difference between the 48-bit and the 32-bit ones that i can
discern is:
* P48R-type has bits 47:43 marked as "imm[11:5] which is probably an error.
* P48FI-type doesn't seem to have a corresponding RV32 type
* P48 LD-type looks like it's the RV32-I-type and P48 ST-type looks like it
is the RV32 S-type as the "base"
however, none of them look like they actually deviate - at all - from the
"normal" RV32 types, meaning that, yes, the same decode hardware can indeed
be used for P48*-type as well as RV32-*type.
that just leaves bits 7 thru 17 in each case to be expanded out to fill 64
(or greater) bits (the priority being the internal representation: an
external one would be "nice to have if possible"), and the task is
completed.
expanding rd, rs1, rs2 and rs3 out to 8 bits: yes, the
rd[5]/rs1[5]/rs2[5]/rs3[5] can fill the "internal" 64-bit representation as
follows (or something like it):
if vs == 0:
rd64[7:0] = {0,0,0,rd[4:0]}
else:
rd64[7:0] = {0,rd[4:0],0,0}
where rd64[7:5] is in the top bits somewhere and rd64[4:0] is in the
*exact* same position - exact same format - as its RV32*-type *and*
P48*-type version.
that takes up 2*4 = 8 of the available spare 16 bits, which leaves room to
expand one (or more) of the other fields, minus one bit if we want to stick
to the RV 64-bit format (first 6 bits == 0b111111), that leaves 7 bits
spare to break out vtp5/vitp6, *if indeed it is necessary* or if there are
not higher priorities.
one of the key important things to be able to do here is to specify VL in
the internal instruction format. it is going to have to be carried anyway,
taken from the "current" copy of the VL CSR.
so the 6 bits of VL are a high priority to carry around: much higher than
adding extra bits to the register numbers.
l.
48-bit Instruction Encodings
============================
In the following table, *Reserved* entries must be zero. RV32 equivalent
encodings
included for side-by-side comparison (and listed below, separately)
+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
| Encoding | 47:43 | 42:41 | 40:36 | 35:31 | 30:28 |
27:23 | 22:18 | 17 | 16 | 15 | 14 | 13 |
12 | 11:7 | 6 | 5:0 |
+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
| RV32 Encoding | 31:27 | 26:25 | 24:20 | 19:15 | 14:12 | 11:7
| 6:2 | 1 | 0 |
|
+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+---------------------------------------------+------+------------+--------+
| P48LD-type | imm[11:0] | rs1[4:0] | width |
rd[4:0] | opcode | rd[5] | rs1[5] | lsk
| vtp5 | *Reserved* | 011111 |
+---------------+---------------------+----------+----------+--------+----------+--------+--------+------------+------------+--------------------------------+------+------------+--------+
| P48ST-type | imm[11:5] | rs2[4:0] | rs1[4:0] | width |
imm[4:0] | opcode | lsk[3] | rs1[5] | rs2[5] | lsk[2:0]
| vtp5 | *Reserved* | 011111 |
+---------------+---------------------+----------+----------+--------+----------+--------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
| RV32-S-type + imm[11:5] + rs2[4:0] + rs1[4:0] + funct3 |
imm[4:0] + opcode + 1 + 1 |
+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
| P48R-type | imm[11:5] | rs2[4:0] | rs1[4:0] | funct3 |
rd[4:0] | opcode | rd[5] | rs1[5] | rs2[5] | vs2 | vs1 |
vitp6 | *Reserved* | 011111 |
+---------------+---------------------+----------+----------+--------+----------+--------+--------+------------+------------+-----+------------+--------------------+------------+--------+
| RV32-R-type + funct7 + rs2[4:0] + rs1[4:0] + funct3 |
rd[4:0] + opcode + 1 + 1 |
+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
| P48I-type | imm[11:0] | rs1[4:0] | funct3 |
rd[4:0] | opcode | rd[5] | rs1[5] | *Reserved* | vd | vs1 |
vitp6 | *Reserved* | 011111 |
+---------------+--------------------------------+----------+--------+----------+--------+--------+------------+------------+-----+------------+--------------------+------------+--------+
| RV32-I-type + imm[11:0] + rs1[4:0] + funct3 |
rd[4:0] + opcode + 1 + 1 |
+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
| P48U-type | imm[31:12] |
rd[4:0] | opcode | rd[5] | *Reserved* | *Reserved* | vd | *Reserved* |
vitp6 | *Reserved* | 011111 |
+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
| RV32-U-type + imm[31:12] |
rd[4:0] + opcode + 1 + 1 |
+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
| P48FR-type | funct7[6:2] | fmt | rs2[4:0] | rs1[4:0] | rm |
rd[4:0] | opcode | rd[5] | rs1[5] | rs2[5] | vs2 | vs1 |
*Reserved* | vtp5 | *Reserved* | 011111 |
+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
| RV32-FR-type + funct5 + fmt + rs2[4:0] + rs1[4:0] + rm |
rd[4:0] + opcode + 1 + 1 |
+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
| P48FI-type | funct7[6:2] | fmt | funct5 | rs1[4:0] | rm |
rd[4:0] | opcode | rd[5] | rs1[5] | *Reserved* | vd | vs1 |
*Reserved* | vtp5 | *Reserved* | 011111 |
+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
| P48FR4-type | rs3[4:0] | fmt | rs2[4:0] | rs1[4:0] | rm |
rd[4:0] | opcode | rd[5] | rs1[5] | rs2[5] | vs2 | rs3[5] |
vs3 [#fr4]_ | vtp5 | *Reserved* | 011111 |
+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
| RV32-FR4-type + rs3[4:0] + fmt + rs2[4:0] + rs1[4:0] + funct3 |
rd[4:0] + opcode + 1 + 1 |
+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
Separately, RV32 encodings:
+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
| Encoding | 31:27 | 26:25 | 24:20 | 19:15 | 14:12 | 11:7
| 6:2 | 1 | 0 |
|
+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
| RV32-R-type + funct7 + rs2[4:0] + rs1[4:0] + funct3 |
rd[4:0] + opcode + 1 + 1 |
+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
| RV32-S-type + imm[11:5] + rs2[4:0] + rs1[4:0] + funct3 |
imm[4:0] + opcode + 1 + 1 |
+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
| RV32-I-type + imm[11:0] + rs1[4:0] + funct3 |
rd[4:0] + opcode + 1 + 1 |
+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
| RV32-U-type + imm[31:12] |
rd[4:0] + opcode + 1 + 1 |
+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
| RV32-FR4-type + rs3[4:0] + fmt + rs2[4:0] + rs1[4:0] + funct3 |
rd[4:0] + opcode + 1 + 1 |
+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
| RV32-FR-type + funct5 + fmt + rs2[4:0] + rs1[4:0] + rm |
rd[4:0] + opcode + 1 + 1 |
+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
More information about the libre-riscv-dev
mailing list