[libre-riscv-dev] uniform instruction format
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun Jun 23 12:51:07 BST 2019
On Sunday, June 23, 2019, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> I got it. I know how svlen and VLtyp (sub vector and Vector in the 48 and
> 64 bit prefixes) can be done, and not adversely affect main spec.
> Give P48 and P64 their own, fully independent SVPSTATE CSR, identical in
> usage, meaning and implementation details to main spec STATE CSR.
Nope. Better solution: share STATE, however make programmer responsible for
saving STATE to temporary reg (or stack) during operation of a batch of
This entirely possible because STATE is context-switch saveable, and
therefor can serve double-duty to protect loops when a batch of P48/P64 ops
use VLtyp or svlen.
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