[libre-riscv-dev] uniform instruction format
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun Jun 23 11:55:50 BST 2019
I got it. I know how svlen and VLtyp (sub vector and Vector in the 48 and
64 bit prefixes) can be done, and not adversely affect main spec.
Give P48 and P64 their own, fully independent SVPSTATE CSR, identical in
usage, meaning and implementation details to main spec STATE CSR.
This has some startling implications, namely that far from being an
override, P48 and P64 are effectively their own independent vectorisation
They can even be embedded inside VLIW formatted instruction groups and
cause nested vectorisation behaviour.
This as opposed to a kind of flat "override", because that can be achieved
If the main VLIW SUBVL value is set, and a P48 opcode is used (with
svlen=1), what happens is that the P48 uses the *main* SUBVL.
If however both are set, you effectively get a DOUBLE dose of
Likewise for VL, if the P48 VL is set *and* main VL is active, you get
NESTED (double-dose) vectorisation.
The interaction however I suspect is going to be particularly weird, such
that I think it may be best to say that either:
* vectorised P48/64 opcodes are NOT permitted in VLIW loops (scalar ones
* VLtyp or svlen must *NOT* be used inside VL loops.
Otherwise it just gets too weird.
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