[libre-riscv-dev] KCP53000B micro-architecture thoughts

Samuel Falvo II sam.falvo at gmail.com
Sun Jun 2 06:52:41 BST 2019

On Sat, Jun 1, 2019 at 12:31 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> samuel:
> https://git.libre-riscv.org/?p=soc.git;a=blob;f=src/experiment/compldst.py;hb=HEAD


I'm working on an implementation for an add/store unit as well (loads
not supported since I don't need it for my minimal test case program).
I'm focusing purely on the computation unit at this point.  It only
supports GO_SUM and GO_WRITE inputs, since it's assumed that the FU
itself manages all the other GO_* and *ABLE signals internally.

For summation type instructions, the sequence of states and strobes is
expected to be ISSUE, READ_PENDING (terminated by GO_READ), GO_SUM,
WRITE_PENDING (terminated by GO_WRITE), in that order.  For store
instructions, it'll be ISSUE, READ_PENDING (terminated via GO_READ),
GO_SUM, CMD_PENDING (terminated by bus), ACK_PENDING (terminated by

Although incomplete, this CU is capable of supporting ADD, ADDI,
AUIPC, SUB, ADDW, ADDIW, and SUBW instructions (the latter 3 requiring
assistance from the register file for 32-bit sign extension).  It just
needs an FU smart enough to know how to drive its various inputs and

Despite its simplicity and incomplete status, it takes my computer
about 3 minutes to fully formally verify the design as it currently

My next steps with my unit is to implement a basic FU for supporting
the summation instructions.

Once *that* is done, then I want to complete the FU logic for driving
a TileLink port, which in turn will inform and complete the CU logic
as well.

Samuel A. Falvo II

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