[libre-riscv-dev] KCP53000B micro-architecture thoughts
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sat Jun 1 20:30:59 BST 2019
ignore "counter", it's for testing purposes (to give some fake delays).
this is a hybrid load, store and add/sub computation unit. it's being
designed to handle immediate add/subs, i've not done sign-extending on
the immediate (yet, should be easy enough).
when in LD mode, the sequence is issue -> go_rd -> go_addr -> go_wr to
cover "latch opcode, latch src1, fetch from mem, store in register".
you would call go_addr "go_bus".
when in ST mode, the sequence is issue -> go_rd -> go_addr -> go_store
when in ADD/SUB mode, the sequence is just issue -> go_rd -> go_write
there is quite a lot of use of Mux to dynamically redirect the inputs
to both the register-latches *and* in one case one of the actual SR
Latches. also, we don't want Go_Addr to be fired when in ADD/SUB
mode, so that's ~ANDed out.
i've yet to put in the logic that connects to the actual memory object
(memory bus), that'll be next.
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