[libre-riscv-dev] System-Wide Complexity Rant (was store computation unit)

[Jacob Lifshay]

On Wed, Jun 5, 2019, 00:14 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Wed, Jun 5, 2019 at 8:09 AM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
> >
> > On Wed, Jun 5, 2019, 00:03 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> > wrote:
> >
> > > Intel is absolutely no different here, they too are restricted to
> around 16
> > > to 32k SRAM until the DRAM is brought up in the absolute minimal way,
> again
> > > you just simply do not witness the process unless you are a coreboot
> > > developer.
> >
> > I recall x86 being able to enable cache-as-ram mode to allow using much
> > more than 16-32k of memory before initializing the dram controllers.
>
> nice.  the joys of having billion-dollar budgets, eh? :)
>
it doesn't actually sound very hard to implement, all you need is a few
muxes in the last-level-cache, which I think we should implement as it
sounds very useful for boot.

Jacob