[libre-riscv-dev] KCP53000B micro-architecture thoughts

Jacob Lifshay programmerjake at gmail.com
Sat Jun 1 00:33:31 BST 2019

On Fri, May 31, 2019, 16:16 Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> In SV we may actually have to do this (cannot say I am looking forward to
> it!) with respect to Vector Length.
> VL is a CSR that completely changes the instruction behaviour at the issue
> phase.
> As in, it actually causes MORE instructions to be issued in a hardware
> for-loop.
> So, setting it causes some intricate critical dependencies that will have
> to be thought through really carefully.
Just do the same thing you'd do for mispredicted branches, cancel all
instructions issued after, then issue the correct instructions.


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