[libre-riscv-dev] KCP53000B micro-architecture thoughts

[Luke Kenneth Casson Leighton]

On Sat, Jun 1, 2019 at 12:33 AM Jacob Lifshay <programmerjake at gmail.com> wrote:

>  > VL is a CSR that completely changes the instruction behaviour at the issue
> > phase.
> >
> > As in, it actually causes MORE instructions to be issued in a hardware
> > for-loop.
> >
> > So, setting it causes some intricate critical dependencies that will have
> > to be thought through really carefully.
> >
> Just do the same thing you'd do for mispredicted branches, cancel all
> instructions issued after, then issue the correct instructions.

 if there was a decision-point (branching-point) that i believe would
be the correct strategy.  however in this case, there are i believe a
few approaches here:

 (1) have issue *decode* Function Units (!!!) which would have *read*
shadows (!!) cast over them, preventing the issue from taking place -
yes prevented from insertion into the instruction queue - until VL is
known.

 (2) have a special "detect" of the VL CSR set, which is
"combinatorial" and takes place actually at the instruction issue
phase, then adding the VL register as a *SECOND* write dependency (as
a second register to be written) to the Function Units that use it,
and having the VL register also as a read dependency (on all FUs that
use it i.e. basically everything).

 (3) stall until every instruction with the "current" VL is out of the
way (committed).

 (4) other.

honestly i'm not totally "Getting It" yet.

l.