[libre-riscv-dev] LD/ST address matcher

[whygee at f-cpu.org]

On 2019-06-05 07:37, Jacob Lifshay wrote:
> Note that texture access is just one of the places that memory is 
> accessed
> in sequence separated by exact multiples of 1 MiB. Other places are
> fetching vertex parameters from multiple separate buffers (Quite 
> common,
> maybe even more than multiple textures), and writing to multiple output
> images. Having texture fetch instructions is still necessary, but we 
> should
> also support loads separated by exact multiples of large powers of 2.
> 
> Note that the inner rendering loop can easily be too big to fit in the
> issue queue, so relying on multiple loop iterations executing at once 
> is a
> non-starter.
> 

Then what about XORing some MSB of the pointers with lower/middle bits 
of the addresses
before lookup in the cache's CAM ?