[libre-riscv-dev] LD/ST address matcher

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Jun 5 13:15:28 BST 2019

On Wed, Jun 5, 2019 at 12:01 PM <whygee at f-cpu.org> wrote:

> Then what about XORing some MSB of the pointers with lower/middle bits
> of the addresses
> before lookup in the cache's CAM ?

 mitch gave an example which demonstrated that if any MSBs are used of
the Virtual Address, the result is, unfortunately, that a mapping to
the (same) physical address will result in a false match.

 thus if we do consider using VA MSBs beyond the 4k boundary (the
point at which VA == PA, guaranteed), we *have* to match against the
VA MSBs *AND* the PA MSBs.

 that means in turn that we are forced to DELAY the AGEN hit/miss
computation until the PA lookup is available.

 this clearly has ramifications that are not only far more complex,
they have an adverse effect on performance.

 hence why i am asking for a full and comprehensive evaluation of the
algorithms to see if the automatic "striping" that would result from
multiple LD/STs being outstanding in the Dep Matrices.

 and why Mitch recommended a completely separate suite of Texture
instructions that perform not just the computation but bypass the AGEN
checks entirely.

 with a completely separate suite of 3D Texture opcodes, there's no
danger, as the opcode computes the LD/ST locations itself, based on
the FP pixel coordinates, and performs interpolation of the Textures
using the fractional part of the FP pixel coords.


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