[libre-riscv-dev] [Bug 92] Implement in order instruction retire refcounting

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Thu Jun 6 22:31:11 BST 2019


--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
bitsmod[i]= retiring[(i + idx)mod 4]

if bitsmod[0] and ~bitsmod[1]:
   idx_inc = 1
elif bitsmod[0] and bitsmod[1] and ~bitsmod[2]:
   idx_inc = 2
elif bitsmod[0] and bitsmod[1] and 
 bitsmod[2] and ~bitsmod[3]:
   idx_inc = 3
elif allset:
    idx_inc= 4# to be modulo 4

Nonzero test on idx_inc determines if commit goes ahead.

Actual inc on round robin is idx_inc mod 4

In this way we know that out of 4 possible commits rhe order will be
maintained, plus we can detect up to 4 simultaneous commits in one cycle.

The multi priority picker may still be needed because we still do not know
which FU is writable. Unless... the shadow stripes are only presenting one per

This might actually work!

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