[libre-riscv-dev] store computation unit

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Jun 21 14:53:39 BST 2019

right.  i think i found it.  2.3.3 of MC88120 book:

2.3.3 Operand Capture
An entry in a Reservation Station corresponds to an instruction in the
Execution Window.
Said instruction may be waiting for operands, or waiting to be picked and
launched into

By recording the data-dependencies in slot and checkpoint notation, one can
use the
*slotfield to control a multiplexer* and only look at one result bus. Thus,
instead of 6
comparators there is only one. This microArchitectural detail saves gates,
area, power,
and complexity.


i think this is the same concept as that round-robin idea i described a
week (or so) ago.  *at issue* time, you pre-allocate (on a round-robin
basis) which of the multiple write register ports that that particular
instruction is going to use when it comes to commit.

in the scheme that i described, as there can only be one of these at a time
(because of the full in-order instruction preservation), you don't even,
strictly speaking, *need* a priority picker *at all*.  you *know* that
there can be only one instruction per register write-port that will be in
"ready to commit" phase, because "ready to commit" phase *inherently*
prevents and prohibits the "shadow" line from clearing across all
later-issued instructions with that same [round-robin-allocated] write-port

interestingly, operand forwarding throws a right-old spanner in the works,
there :)


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