[libre-riscv-dev] System-Wide Complexity Rant (was store computation unit)

Jacob Lifshay programmerjake at gmail.com
Wed Jun 5 08:09:25 BST 2019

On Wed, Jun 5, 2019, 00:03 Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> Intel is absolutely no different here, they too are restricted to around 16
> to 32k SRAM until the DRAM is brought up in the absolute minimal way, again
> you just simply do not witness the process unless you are a coreboot
> developer.

I recall x86 being able to enable cache-as-ram mode to allow using much
more than 16-32k of memory before initializing the dram controllers.

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