[libre-riscv-dev] [Bug 44] IEEE754 FPU inverse-sqrt

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=44

--- Comment #32 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #31)
> If no one else is working on it, I'll start working on implementing the
> div/mod/fdiv/fsqrt/frsqrt pipeline.

keep it short, keep in touch continously (every few days), and use .pyi files,
do *not* put type information into the .py files, and for FP, follow the
format of the pipeline code rather than create an entirely new pipeline design
(use FPMUL and FPADD as cookie-cut templates).  otherwise we waste time
and money reworking two sets of completely disparate code.

also keep the integer and FP pipelines *separate* for now: the FPU code
is seriously complicated already, and in actual usage, int would hold up FP
and FP would hold up int.

i'm looking to put in another funding application to cover a "comprehensive"
version of the isqrt/fsqrt/fdiv code, including formal verification, for
which programmer-mathematicians could be attracted to help out.

that means keeping the timescales on FPDIV/ISQRT/SQRT *real* short.

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