[libre-riscv-dev] [Bug 78] IEEE754 FP "div" needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=78

Jacob Lifshay <programmerjake at gmail.com> changed:

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--- Comment #3 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #2)
> > FDIV is often implemented with a FRECIP
> > (reciprocal) followed by a FMUL.
We can't use FRECIP followed by FMUL without additional intermediate precision
since the RISCV spec requires FDIV to have correctly rounded results.
> 
> we *might* need a pipelined fdiv, yet to be evaluated.  where in a
> standard processor, time is not really critical, for a GPU it definitely
> is.
> 
> FSQRT and ISQRT are definitely going to be done as pipelines, jacob knows
> if we need FDIV to be pipelined.
having a pipelined fdiv is more important than sqrt or rsqrt, since divisions
are much more common (every pixel needs at least 1 division)
> 
> if an FRECIP can be tracked down and it can be done as a pipeline
> (that's if we need DIV to be pipelined), that would be good.

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