[libre-riscv-dev] [Bug 78] IEEE754 FP "div" needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=78

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
> FDIV is often implemented with a FRECIP
> (reciprocal) followed by a FMUL.

we *might* need a pipelined fdiv, yet to be evaluated.  where in a
standard processor, time is not really critical, for a GPU it definitely
is.

FSQRT and ISQRT are definitely going to be done as pipelines, jacob knows
if we need FDIV to be pipelined.

if an FRECIP can be tracked down and it can be done as a pipeline
(that's if we need DIV to be pipelined), that would be good.

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