[libre-riscv-dev] [Bug 44] IEEE754 FPU inverse-sqrt

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=44

--- Comment #35 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-riscv.org/?p=ieee754fpu.git;a=commitdiff;h=ca5cce9412df04c5887387c9efe7b5f87082fce0

done.  copied FPMUL's specialcases.py, sat it side-by-side with
ieee754/fpdiv/nmigen_div_experiment.py.

untested: it doesn't have syntax errors.

btw there's no version of ieee754/fpmul/test/test_fpmul_pipe.py
yet, because there's only the FSM-based (jon dawson) variant of
FPDIV, not a corresponding pipelined version.

test_fpmul_pipe.py is the template to use to start creating an
FPDIV... actually, it's such an easy cookie-cut i might as
well do it: that will be ieee754/fpdiv/pipeline.py

then instead of from .mulstages import FPMulStages
that would be:

from .divstages import FPDivStages

and that's literally the only class that's needed to get an
operational FPDIV multi-in, multi-out Reservations-Style pipeline
up and running.

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